The present invention relates to an operation of a nonvolatile memory device and, more particularly, to a method of verifying programming of a nonvolatile memory device using a double verify method.
A semiconductor memory device is a memory device in which data can be stored and from which stored data can be read. Semiconductor memory devices include volatile memory, which loses its stored data when power is off, and nonvolatile memory, which can retain its stored data although power is off. Flash memory of the nonvolatile memories electrically erases data of cells as a group and is widely used in computers, memory cards, etc.
Flash memory is categorized into a NOR type and a NAND type according to the connection status of cells and bit lines. NOR type flash memory has a structure in which two or more cell transistors are connected in parallel to one bit line. NOR type flash memory is configured to store data using the channel hot electron scheme and erase data using the Fowler-Nordheim (F-N) tunneling scheme. NAND type flash memory has a structure in which two or more cell transistors are connected in series to one bit line. NAND type flash memory is configured to store and erase data using the F-N tunneling scheme. In general, NOR type flash memory is disadvantageous for high integration because of large current consumption, but is advantageous for high speed. NAND type flash memory is advantageous for high integration because it uses a cell current lower than that of NOR type flash memory.
A method of programming a nonvolatile memory device includes an incremental step pulse programming (ISPP) scheme. In the ISPP scheme, after applying a program pulse, a program voltage is only applied to memory cells having a threshold voltage level lower than a verify voltage level, while increasing the program voltage by a certain step. Memory cells having threshold voltage distributions higher than the verify voltage level are program-inhibited.
If a lower step voltage is set with respect to memory cells having a specific program speed, the width of threshold voltage distributions can be narrowed. However, if the step voltage is set to a low level, the program time increases. In contrast, if the step voltage is set to a high level, the program time decreases, but the width of threshold voltage distributions of memory cells is increased.
When verifying programming in a nonvolatile memory device, a variety of methods of narrowly forming threshold voltage distributions of memory cells have been proposed.